1. Field of Invention
The field of the present invention relates in general to analog-to-digital (A/D) conversion. More particularly the present invention relates to a multi-stage multi-channel A/D converter.
2. Description of the Related Art
Analog-to-digital (A/D) converters are used in a wide variety of applications including telecommunications, radar, medical imaging, seismology, etc. There are numerous architectures for implementing A/D conversion including: flash, multi-step, pipeline, interpolating, and successive approximation The pipelined technique offers reduced circuit complexity, and power consumption with relatively high throughput. Several of these designs are shown in FIGS. 1A-C.
FIG. 1A is a block diagram of a prior art pipelined A/D converter 100 with three stages. In a pipelined architecture, the first stage operates on the most recent sample inputted while subsequent stages operate on residues from the prior samples output from prior stages of the cascaded pipeline architecture. The A/D converter includes a sample and hold unit 106; first, second, and third stages respectively 110, 120, 130; and a common clock 108. Each stage makes a digital approximation of the amplitude of the analog sample presented to it and passes the amplified residue to the next stage where the process is repeated for the next most significant bits. In operation, an analog signal (e.g., channel 1) on line 102 is delivered to a first sample and hold element 106. The first stage makes the digital approximation of the most significant bits of the sampled signal and delivers that on bit line 112. The amplified residue is presented on signal line 114 to the intermediate stage 120. The intermediate stage generates a digital approximation of the most significant bits of the residue signal, which in this case corresponds to the intermediate significant bits of the sample obtained from channel 1. These intermediate significant bits are output on bit line 122 and the amplified residue is output on signal line 124. Signal line 124 provides the input to the final stage 130 which generates a digital signal corresponding to the most significant bits of the residue. These bits correspond with the least significant bits of the original sample of channel 1. These are output on bit line 132. The composite signal in serial or parallel form with a precision determined by the combined signals on bit lines 112, 122, and 132 is presented on digital signal line 104. The common clock 108 drives each of the above-discussed components in a synchronous relationship. Each operates at the same clock speed.
As shown in FIG. 1B, each stage contains a sample and hold (SH) 158, an A/D converter (ADC) 150, a digital-to-analog converter (DAC) 156, and a differencer 154. The functions implemented by the DAC, SH and differencer may be implemented by a multiplying digital-to-analog converter (MDAC) 152. Both the ADC 150 and the differencer 154 are coupled directly to the analog signal line 114. The ADC 150 generates a signal corresponding the most significant bits of the signal received on signal line 114. This signal is provided as an output on bit line 122 as well as an input to the DAC 156. The DAC converts these most significant bits to analog form and provides them to the negative input of differencer 154. The differencer outputs a residue signal corresponding to the difference between the input signal on line 114 and the most significant bits generated by ADC 150 on bit line 122. The output of the summer is identified as a residue which is passed to the SH device 158 for output on signal line 124. The SH device includes a gain element to amplify the residue.
FIG. 1C shows a variation on the above mentioned pipelined designs. In this design the second stage works on the same signal as the first, rather than the residue of the first. Both stages accept input from the sample and hold 106. In this second design the source and sink voltages used by the second stage flash A/D converter are adjusted to a voltage window determined by the first stage. For example, if the first stage determines the sampled voltage level is between 1.2 and 1.1 volts then the second stage source and sink voltages respectively would be set to those levels by a driver 180 coupled between the first and second stages. Thus the second stage would have higher resolution than the first over a more limited range. As each new voltage is sampled the most significant bits (MSB""s) of that digital voltage approximation are supplied on line 112 from the first stage. This same information received by the driver results in the alteration of source and sink voltages of the second stage by signals sent from the driver. The second stage determines the digital least significant bits (LSBs) of the input signal and passes those on signal line 184 to logic for combining the MSB from the first stage with the LSB from the second.
The main advantage of these pipelined ADCs are that they can provide high throughput rates and occupy small die areas when implemented in an integrated circuit. Both advantages stem from the concurrent operation of the stages; that is, at any time the first stage operates on the most recent sample, while all other stages operate on residues from previous samples. If the A/D are done with flash converters, pipelined architectures require only two main clock phases per conversion; therefore the maximum throughput rate can be high. Also, since the stages operate concurrently, the number of stages used to obtain a given resolution is not constrained by the required throughput rate.
For multi-channel applications, prior art pipelined A/D converters require proportionately larger die areas and have concurrently larger power dissipations.
What is needed is a A/D converter architecture with reduced die area and power dissipation for multi-channel applications.
An apparatus and method for A/D conversion is provided. The apparatus provides for multi-channel A/D conversion. It may be used in any application in which high speed A/D conversion of either a single signal or multiple signal sources is required. Such applications include X-DSL communications. The apparatus and method allows A/D converters to be fabricated with a reduced form cost and power factors when compared with prior art designs.
In an embodiment of the invention an A/D converter for obtaining digital samples from a plurality of analog information signals is disclosed. The A/D converter comprises a sampler, a converter and a logic. The sampler includes an input and an output, and the input coupled with the at least one analog information signal. The sampler repetitively provides at least, one pre-sample together with a sample of the at least one analog information signal. The sampling interval between the samples for an selected analog information signal is substantially greater than a pre-sample interval between the at least one pre-sample and the corresponding sample for the selected analog information signal. The converter includes a bit line output and at least one input coupled with the output of said sampler. The converter is responsive to the at least one pre-sample at the input to output a first bit signal corresponding to at least one significant bit of the at least one pre-sample at the bit line output. The converter is further responsive to the sample at the input, to output a second bit signal corresponding to at least one significant bit of the sample at the bit line output. The logic is coupled with the bit line output of said converter. The logic combines the first bit signal and the second bit signal into a composite digital sample of the at least one pre-sample together with the sample.
In an alternate embodiment of the invention a method for obtaining digital samples from at least one analog information signal is disclosed. The method comprises the acts of:
repetitively providing at least one pre-sample together with a sample of the at least one analog information signal, and with a sampling interval between the samples of the at least one analog information signal substantially greater than a pre-sample interval between the at least one pre-sample and the corresponding sample;
generating a first bit signal and a second bit signal, with the first bit signal corresponding to at least one significant bit of the at least one pre-sample at the bit line output, and the second bit signal corresponding to at least one significant bit of the sample at the bit line output; and
combining the first bit signal and the second bit signal into a composite digital sample of the at least one pre-sample together with the sample.